1. Field of the Invention
The invention relates to a package structure and a packaging method of a chip, and more particularly, relates to a package structure and a packaging method of wafer level chip scale package.
2. Description of Related Art
With electronic devices popularized in recent years, portable and wearable electronic devices have become important tools in daily lives. Accordingly, it becomes a necessary trend to develop electronic products and elements which include features such as high performance, compact volume, high computation speed, high quality and multifunction. In terms of appearance, a necessary trend thereof is to develop electronic products which are light, thin and compact. In order to meet the requirements of the trends, use of a packaging process of the wafer level chip scale package (WLCSP) becomes one of the necessary choices.
A major difference between the wafer level chip scale package and the traditional packing technology is that, a concept of wafer level chip scale package is to complete packaging of integrated circuits directly on the wafer instead of performing the packaging process for individual chip after being cut. By using the wafer level chip scale package, a dimension of a packaged chip is identical to a dimension of the original die. However, said dimension in the wafer level chip scale package will restrict a range for arranging fan-out. Accordingly, a packaging technology so-called wafer level chip scale package for fan-out has been proposed in the industry. By using the packaging technology of the wafer level chip scale package for fan-out, the packaged chip is capable of providing diverse and flexible wiring schemes, and making an adhesion between a chip and a printed circuit board easier to execute, so as to improve a production yield thereof.